In a semiconductor integrated circuit chip, a power source voltage different from that of an external I/O is often used for low power consumption. On the other hand, an external input reception circuit in the semiconductor integrated circuit chip often uses the same power source voltage as that of the external I/O. Therefore, in the semiconductor integrated circuit chip, it is required to convert a voltage of a signal in the chip by use of a level shift circuit.
The conventional level shift circuit that level-shifts a signal of a VEXTQ (external) power source system to a signal of a VDD (internal) power source system includes a level shifter of a VDD power source system, an inverter of a VEXTQ power source system and an inverter of a VDD power source system.
The level shifter includes an input-side circuit provided between a VDD power source voltage supply node and a VSS ground voltage supply node and an output-side circuit provided between the VDD power source voltage supply node and the VSS ground voltage supply node. The input-side circuit includes first and second PMOS transistors and an NMOS transistor serially connected in a direction from the VDD power source voltage supply node to the VSS ground voltage supply node. The common connection drain terminal of the drain terminal of the second PMOS transistor and the drain terminal of the NMOS transistor forms an output node of the input-side circuit. Input signal IN is input to the gates of the first PMOS transistor and the NMOS transistor. Input signal IN is also input to the gate of the inverter of the VEXTQ power source system. The output-side circuit of the level shifter has the same configuration as that of the input-side circuit and includes first and second PMOS transistors and an NMOS transistor serially connected in a direction from the VDD power source voltage supply node to the VSS ground voltage supply node. The common connection drain terminal of the drain terminal of the second PMOS transistor and the drain terminal of the NMOS transistor forms an output node of the output-side circuit. An output signal (a level inversion signal of input signal IN) from the inverter of the VEXTQ power source system is input to the gates of the first PMOS transistor and the NMOS transistor of the output-side circuit. The gate of the second PMOS transistor of the input-side circuit and the gate of the second PMOS transistor of the output-side circuit are cross-coupled. That is, the gate of the second PMOS transistor of the input-side circuit is connected to the drain terminal of the second PMOS transistor of the output-side circuit and the gate of the second PMOS transistor of the output-side circuit is connected to the drain terminal of the second PMOS transistor of the input-side circuit.
In the conventional level shift circuit, a time required for input signal IN to be input and output, that is, transition time is different when the output node of the output-side circuit of the level shifter is set to “H” and when it is set to “L”. Specifically, when input signal IN falls to “L”, the output node of the inverter becomes “H” and the NMOS transistor of the output-side circuit of the level shifter is turned on to set the output node of the output-side circuit to “L”, the transition time is short. On the other hand, when input signal IN rises to “H” and the output node of the output-side circuit of the level shifter is set to “H”, the PMOS transistor of the output-side circuit is not turned on if the output node of the input-side circuit is lowered towards “L” to some extent. Therefore, when the output node of the output-side circuit is set to “H”, the transition time becomes slightly longer. As a result, the transition time of output signal OUT output from the inverter of the VDD power source system becomes different.
Thus, in the conventional level shift circuit, a difference occurs in the transition time at the rise time and fall time of the input signal. If the transition time of a signal of the level shift circuit is different at the rise time and fall time of the input signal, it becomes necessary to set an excessive margin of setup/hold or the like in the I/O of an external device and the performance of the external device is degraded.
In Jpn. Pat. Appln. KOKAI Publication No. 2004-363843, a level shift circuit that enhances the performance of a conversion operation by connecting a large number of level shifters to a large number of different power source voltages and gradually shifting the signal level to decrease a conversion potential difference between the respective level shifters is described.